MPC5604B/C Microcontroller Reference Manual, Rev. 8
600 Freescale Semiconductor
If a normal conversion is ongoing and a CTU conversion is triggered, then any ongoing channel conversion
is aborted and the CTU triggered conversion is processed. When it is finished, the normal conversion
resumes from the channel at which the normal conversion was aborted.
If another CTU conversion is triggered before the end of the conversion, that request is discarded.
When a normal conversion is requested during CTU conversion (CTUSTART bit = ‘1’), the normal
conversion starts when CTU conversion is completed (CTUSTART = ‘0’). Otherwise, when an Injected
conversion is requested during CTU conversion, the injected conversion is discarded and the
MCR[JSTART] is immediately reset.
25.3.5 Presampling
25.3.5.1 Introduction
Presampling is used to precharge or discharge the ADC internal capacitor before it starts sampling of the
analog input coming from the input pins. This is useful for resetting information regarding the last
converted data or to have more accurate control of conversion speed. During presampling, the ADC
samples the internally generated voltage.
Presampling can be enabled/disabled on a channel basis by setting the corresponding bits in the PSR
registers.
After enabling the presampling for a channel, the normal sequence of operation will be
Presampling + Sampling + Conversion for that channel. Sampling of the channel can be bypassed by
setting the PRECONV bit in the PSCR. When sampling of a channel is bypassed, the sampled data of
internal voltage in the presampling state is converted (Figure 25-5, Figure 25-6).
Figure 25-5. Presampling sequence
Figure 25-6. Presampling sequence with PRECONV = 1
25.3.5.2 Presampling channel enable signals
It is possible to select between two internally generated voltages V0 and V1 depending on the value of the
PSCR[PREVAL] as shown in Table 25-4.
Presampling is enabled in the channel C and D. For channel B total conversion clock cycles = (S) + (C).
For channel C and D total conversion clock cycles = (P) + (S) + (C).
Sample B Convert B Presample C Convert C Presample D Sample D Convert DSample C Sample E
Sample B Convert B Presample C Presample D Convert D Sample E Convert EConvert C
Presampling enabled in channel C and D but sampling is bypassed in these channels by setting PRECONV = 1 in the PSCR.
For channel C and D total conversion clock cycles = (P) + (C).
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