Freescale Semiconductor MPC5604B - Fast Internal RC Oscillator (FIRC) Digital Interface

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 101
6.6 Fast internal RC oscillator (FIRC) digital interface
6.6.1 Introduction
The FIRC digital interface controls the 16 MHz fast internal RC oscillator (FIRC). It holds control and
status registers accessible for application.
6.6.2 Functional description
The FIRC provides a high frequency (f
FIRC
) clock of 16 MHz. This clock can be used to accelerate the exit
from reset and wakeup sequence from low power modes of the system. It is controlled by the MC_ME
module based on the current device mode. The clock source status is updated in ME_GS[S_RC]. Please
refer to the MC_ME chapter for further details.
The FIRC can be further divided by a configurable division factor in the range from 1 to 32 to generate the
divided clock to match system requirements. This division factor is specified by RC_CTL[RCDIV] bits.
The FIRC output frequency can be trimmed using FIRC_CTL[FIRCTRIM]. After a power-on reset, the
FIRC is trimmed using a factory test value stored in test flash memory. However, after a power-on reset
the test flash memory value is not visible at FIRC_CTL[FIRCTRIM], and this field will show a value of
zero. Therefore, be aware that the FIRC_CTL[FIRCTRIM] field does not reflect the current trim value
until you have written to it. Pay particular attention to this feature when you initiate a read-modify-write
operation on FIRC_CTL, because a FIRCTRIM value of zero may be unintentionally written back and this
may alter the FIRC frequency. In this case, you should calibrate the FIRC using the CMU or ensure that
you write only to the upper 16 bits of this FIRC_CTL.
In this oscillator, two's complement trimming method is implemented. So the trimming code increases
from –32 to 31. As the trimming code increases, the internal time constant increases and frequency
reduces. Please refer to device datasheet for average frequency variation of the trimming step.
During STANDBY mode entry process, the FIRC is controlled based on ME_STANDBY_MC[RCON]
bit. This is the last step in the standby entry sequence. On any system wake-up event, the device exits
STANDBY mode and switches on the FIRC. The actual powerdown status of the FIRC when the device
is in standby is provided by RC_CTL[FIRCON_STDBY] bit.
S_SIRC SIRC clock status.
0 SIRC is not providing a stable clock.
1 SIRC is providing a stable clock.
SIRCON_STDBY SIRC control in STANDBY mode.
0 SIRC is switched off in STANDBY mode.
1 SIRC is switched on in STANDBY mode.
Table 6-6. SIRC_CTL field descriptions (continued)
Field Description