MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 789
The boundary scan register is external to JTAGC but can be accessed by JTAGC TAP through
EXTEST,SAMPLE,SAMPLE/PRELOAD instructions. The functionality of each TEST mode is
explained in more detail in Section 32.8.4, “JTAGC instructions.
32.5.2.1 Bypass Mode
When no test operation is required, the BYPASS instruction can be loaded to place the JTAGC into bypass
mode. While in bypass mode, the single-bit bypass shift register is used to provide a minimum-length
serial path to shift data between TDI and TDO.
32.5.2.2 TAP sharing mode
There are three selectable auxiliary TAP controllers that share the TAP with the JTAGC. Selectable TAP
controllers include the Nexus port controller (NPC) and PLATFORM. The instructions required to grant
ownership of the TAP to the auxiliary TAP controllers are ACCESS_AUX_TAP_NPC,
ACCESS_AUX_TAP_ONCE, ACCESS_AUX_TAP_TCU. Instruction opcodes for each instruction are
shown in Table 32-3.
When the access instruction for an auxiliary TAP is loaded, control of the JTAG pins is transferred to the
selected TAP controller. Any data input via TDI and TMS is passed to the selected TAP controller, and any
TDO output from the selected TAP controller is sent back to the JTAGC to be output on the pins. The
JTAGC regains control of the JTAG port during the UPDATE-DR state if the PAUSE-DR state was
entered. Auxiliary TAP controllers are held in RUN-TEST/IDLE while they are inactive.
For more information on the TAP controllers refer to the Nexus port controller chapter of the reference
manual.
32.6 External signal description
The JTAGC consists of four signals that connect to off-chip development tools and allow access to test
support functions. The JTAGC signals are outlined in Table 32-1:
The JTAGC pins are shared with GPIO. TDO at reset is a input pad and output direction control from
JTAGC. Once TAP enters shift-ir or shift-dr then output direction control from JTAGC which allows the
value to see on pad. It is up to the user to configure them as GPIOs accordingly, in this case MPC5604B
get incompliance with IEEE 1149.1-2001.
Table 32-1. JTAG signal properties
Name I/O Function Reset State
TCK I Test clock Pull Up
TDI I Test data in Pull Up
TDO O Test data out High Z
TMS I Test mode select Pull Up
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