Freescale Semiconductor MPC5604B - Protection of Mode Configuration Registers

MPC5604B/C Microcontroller Reference Manual, Rev. 8
182 Freescale Semiconductor
8.4.4 Protection of Mode Configuration Registers
While programming the mode configuration registers ME_<mode>_MC, the following rules must be
respected. Otherwise, the write operation is ignored and an invalid mode configuration interrupt may be
generated.
• FIRC must be on if the system clock is one of the following:
— 16 MHz int. RC osc.
— div. 16 MHz int. RC osc.
• FXOSC must be on if the system clock is one of the following:
— 4-16 MHz ext. xtal osc.
— div. ext. xtal osc.
NOTE
Software must ensure to switch on the clock source that provides the input
reference clock to the FMPLL. There is no automatic protection mechanism
to check this in the MC_ME.
• FMPLL must be on if the system clock is the freq. mod. PLL.
• Configuration “00” for the CFLAON and DFLAON bit fields are reserved.
• MVREG must be on if any of the following is active:
—FMPLL
—CFLASH
—DFLASH
• System clock configurations marked as ‘reserved’ may not be selected.
• Configuration “1111” for the SYSCLK bit field is allowed only for the STOP and TEST modes,
and only in this case may all system clock sources be turned off.
CAUTION
If the system clock is stopped during TEST mode, the device can exit only
via a system reset.
8.4.5 Mode Transition Interrupts
The following are the three interrupts related to mode transition implemented in the MC_ME.
8.4.5.1 Invalid Mode Configuration Interrupt
Whenever a write operation is attempted to the ME_<mode>_MC registers violating the protection rules
mentioned in the Section 8.4.4, “Protection of Mode Configuration Registers, the interrupt pending bit
I_ICONF of the ME_IS register is set and an interrupt request is generated if the mask bit M_ICONF of
ME_IM register is ‘1’.