Freescale Semiconductor MPC5604B - Analog Clock Generator and Conversion Timings

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 597
scan mode is enabled, a new chain conversion is started. The EOC interrupt of the current aborted
conversion is not generated but an ECH interrupt is generated to signal the end of the chain.
When a chain conversion abort is requested (ABORTCHAIN bit is set) while an injected
conversion is running over a suspended Normal conversion, both injected chain and Normal
conversion chain are aborted (both the NSTART and JSTART bits are also reset).
25.3.2 Analog clock generator and conversion timings
The clock frequency can be selected by programming the MCR[ADCLKSEL]. When this bit is set to ‘1’
the ADC clock has the same frequency as the peripheral set 3 clock. Otherwise, the ADC clock is half of
the peripheral set 3 clock frequency. The ADCLKSEL bit can be written only in power-down mode.
When the internal divider is not enabled (ADCCLKSEL = 1), it is important that the associated clock
divider in the clock generation module is ‘1’. This is needed to ensure 50% clock duty cycle.
The direct clock should basically be used only in low power mode when the device is using only the
16 MHz fast internal RC oscillator, but the conversion still requires a 16 MHz clock (an 8 MHz clock is
not fast enough).
In all other cases, the ADC should use the clock divided by two internally.
25.3.3 ADC sampling and conversion timing
In order to support different loading and switching times, several different Conversion Timing registers
(CTR) are present. There is one register per channel type. INPLATCH and INPCMP configurations are
limited when the system clock frequency is greater than 20 MHz.
When a conversion is started, the ADC connects the internal sampling capacitor to the respective analog
input pin, allowing the capacitance to charge up to the input voltage value. The time to load the capacitor
is referred to as sampling time. After completion of the sampling phase, the evaluation phase starts and all
the bits corresponding to the resolution of the ADC are estimated to provide the conversion result.
The conversion times are programmed via the bit fields of the CTR. Bit fields INPLATCH, INPCMP and
INPSAMP are used to define the total conversion duration (T
conv
) and in particular the partition between
sampling phase duration (T
sample
) and total evaluation phase duration (T
eval
).
25.3.3.1 ADC_0
Figure 25-4 represents the sampling and conversion sequence.