Freescale Semiconductor MPC5604B - Register Map

MPC5604B/C Microcontroller Reference Manual, Rev. 8
864 Freescale Semiconductor
Priority Select Register INTC_PSR196_199 32-bit Base + 0x0104
Priority Select Register INTC_PSR200_203 32-bit Base + 0x0108
Priority Select Register INTC_PSR204_207 32-bit Base + 0x010C
Priority Select Register INTC_PSR208_210 32-bit Base + 0x0110
DSPI_0 0xFFF9_0000
Module Configuration Register PMCR 32-bit Base + 0x0000
Reserved — — (Base + 0x0004) –
(Base + 0x0007)
Transfer Count Register TCR 32-bit Base + 0x0008
Clock and Transfer Attribute Registers CTAR0 32-bit Base + 0x000C
Clock and Transfer Attribute Registers CTAR1 32-bit Base + 0x0010
Clock and Transfer Attribute Registers CTAR2 32-bit Base + 0x0014
Clock and Transfer Attribute Registers CTAR3 32-bit Base + 0x0018
Clock and Transfer Attribute Registers CTAR4 32-bit Base + 0x001C
Clock and Transfer Attribute Registers CTAR5 32-bit Base + 0x0020
Reserved — — (Base + 0x0024) –
(Base + 0x0028)
Status Register SR 32-bit Base + 0x002C
DSPI Interrupt Request Enable Register RSER 32-bit Base + 0x0030
PUSH TX FIFO Register PUSHR 32-bit Base + 0x0034
POP RX FIFO Register POPR 32-bit Base + 0x0038
DSPI Transmit FIFO Registers TXFR0 32-bit Base + 0x003C
DSPI Transmit FIFO Registers TXFR1 32-bit Base + 0x0040
DSPI Transmit FIFO Registers TXFR2 32-bit Base + 0x0044
DSPI Transmit FIFO Registers TXFR3 32-bit Base + 0x0048
Reserved — — (Base + 0x004C) –
(Base + 0x007B)
Receive FIFO Registers RXFR0 32-bit Base + 0x007C
Receive FIFO Registers RXFR1 32-bit Base + 0x0080
Receive FIFO Registers RXFR2 32-bit Base + 0x0084
Receive FIFO Registers RXFR3 32-bit Base + 0x0088
Reserved — — (Base + 0x008C) –
(Base + 0x3FFF)
DSPI_1 0xFFF9_4000
Table A-2. Detailed register map (continued)
Register description Register name
Used
size
Address