MPC5604B/C Microcontroller Reference Manual, Rev. 8
602 Freescale Semiconductor
The lower and higher threshold values for the analog watchdog are programmed using the registers
THRHLR.
For example, if channel number 3 is to be monitored with threshold values in THRHLR1, then the
TRC[THRCH] is programmed to select channel number 3.
A set of threshold registers (THRHLRx and TRCx) can be linked only to a single channel for a particular
THRCH value. If another channel is to be monitored with same threshold values, then the TRCx[THRCH]
has to be programmed again.
NOTE
If the higher threshold for the analog watchdog is programmed lower than
the lower threshold and the converted value is less than the lower threshold,
then the WDGxL interrupt for the low threshold violation is set, else if the
converted value is greater than the lower threshold (consequently also
greater than the higher threshold) then the interrupt WDGxH for high
threshold violation is set. Thus, the user should avoid that situation as it
could lead to misinterpretation of the watchdog interrupts.
25.3.7 Interrupts
The ADC generates the following maskable interrupt signals:
• ADC_EOC interrupt requests
— EOC (end of conversion)
— ECH (end of chain)
— JEOC (end of injected conversion)
— JECH (end of injected chain)
— EOCTU (end of CTU conversion)
• WDGxL and WDGxH (watchdog threshold) interrupt requests
Interrupts are generated during the conversion process to signal events such as End Of Conversion as
explained in register description for CEOCFR[0..2]. Two registers named CEOCFR[0..2] (Channel
Pending Registers) and IMR (Interrupt Mask Register) are provided in order to check and enable the
interrupt request to INT module.
Interrupts can be individually enabled on a channel by channel basis by programming the CIMR (Channel
Interrupt Mask Register).
Several CEOCFR[0..2] are also provided in order to signal which of the channels’ measurement has been
completed.
The analog watchdog interrupts are handled by two registers WTISR (Watchdog Threshold Interrupt
Status Register) and WTIMR (Watchdog Threshold Interrupt Mask Register) in order to check and enable
the interrupt request to the INTC module. The Watchdog interrupt source sets two pending bits WDGxH
and WDGxL in the WTISR for each of the channels being monitored.
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