MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 241
All of the external interrupt pads within a single group have equal priority. It is the responsibility of the
user software to search through the group of sources in the most appropriate way for their application.
NOTE
Glitch filter control and pad configuration should be done while the external
interrupt line is disabled in order to avoid erroneous triggering by glitches
caused by the configuration process itself.
12.5.3.1 External interrupt management
Each external interrupt can be enabled or disabled independently. This can be performed using a single
rolled up register (Figure 12-5). A pad defined as an external interrupt can be configured by the user to
recognize external interrupts with an active rising edge, an active falling edge or both edges being active.
NOTE
Writing a ‘0’ to both IREE[x] and IFEE[x] disables the external interrupt
functionality for that pad completely (that is, no system wakeup or interrupt
will be generated on any activity on that pad)!
The active IRQ edge is controlled by the users through the configuration of the registers WIREER and
WIFEER.
Each external interrupt supports an individual flag which is held in the flag register (WISR). The bits in
the WISR[EIF] field are cleared by writing a ‘1’ to them; this prevents inadvertent overwriting of other
flags in the register.
12.5.4 On-chip wakeups
The Wakeup Unit supports two on-chip wakeup sources. It combines the on-chip wakeups with the
external ones to generate a single wakeup to the system.
12.5.4.1 On-chip wakeup management
In order to allow software to determine the wakeup source at one location, on-chip wakeups are reported
along with external wakeups in the WISR register (see Figure 12-4 for details). Enabling and clearing of
these wakeups are done via the on-chip wakeup source’s own registers.
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