Freescale Semiconductor MPC5604B - Chapter 2 Chip-Level Features

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 33
2.2.3 Chip-level features
On-chip modules available within the family include the following features:
• Single issue, 32-bit CPU core complex (e200z0)
— Compliant with the Power Architecture™ embedded category
— Includes an instruction set enhancement allowing variable length encoding (VLE) for code size
footprint reduction. With the optional encoding of mixed 16-bit and 32-bit instructions, it is
possible to achieve significant code size footprint reduction.
• Up to 512 Kbytes on-chip Code Flash supported with the Flash controller
• Up to 64 Kbytes on-chip Data Flash supported with the Flash controller
• Up to 48 Kbytes on-chip SRAM
• Memory protection unit (MPU) with 8 region descriptors and 32-byte region granularity
• Interrupt controller (INTC) capable of handling 148 selectable-priority interrupt sources
• Frequency-modulated phase-locked loop (FMPLL)
• Crossbar switch architecture for concurrent access to peripherals, Flash, or SRAM from multiple
bus masters
• Boot assist module (BAM) supports internal Flash programming via a serial link (FlexCAN or
LINFlex)
• Timer supports input/output channels providing a range of 16-bit input capture, output compare,
and pulse width modulation functions (eMIOS)
• 10-bit analog-to-digital converter (ADC)
• Up to 3 serial peripheral interface (DSPI) modules
• Up to 4 serial communication interface (LINFlex) modules
— LINFlex 1, 2 and 3: Master capable
— LINFlex 0: Master capable and slave capable
• Up to 6 enhanced full CAN (FlexCAN) modules with 64 configurable message buffers
• 1 inter-integrated circuit (I
2
C) module
• Up to 123 configurable general purpose pins supporting input and output operations (package
dependent)
• Real time counter (RTC) with clock source from FIRC or SIRC supporting autonomous wake-up
with 1-ms resolution with max timeout of 2 seconds
— Support for RTC with clock source from SXOSC, supporting wake-up with 1-sec resolution
and max timeout of 1 hour
• 6 periodic interrupt timers (PIT) with 32-bit counter resolution
• 1 system module timer (STM)
• Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class Two Plus
• Device/board boundary scan testing supported with per Joint Test Action Group (JTAG) of IEEE
(IEEE 1149.1)
• On-chip voltage regulator (VREG) for regulation of input supply for all internal levels