MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 547
24.4.4 Functional description
The five types of channels of the eMIOS can operate in the modes as listed in Figure 24-7. The eMIOS
provides independently operating unified channels (UC) that can be configured and accessed by a host
MCU. Up to four time bases can be shared by the channels through four counter buses and each unified
channel can generate its own time base. The eMIOS block is reset at positive edge of the clock
(synchronous reset). All registers are cleared on reset.
24.4.4.1 Unified Channel (UC)
Each Unified Channel consists of:
• Counter bus selector, which selects the time base to be used by the channel for all timing functions
• A programmable clock prescaler
• Two double buffered data registers A and B that allow up to two input capture and/or output
compare events to occur before software intervention is needed.
• Two comparators (equal only) A and B, which compares the selected counter bus with the value in
the data registers
• Internal counter, which can be used as a local time base or to count input events
• Programmable input filter, which ensures that only valid pin transitions are received by channel
• Programmable input edge detector, which detects the rising, falling or either edges
• An output flip-flop, which holds the logic level to be applied to the output pin
• eMIOS Status and Control register
24.4.4.1.1 UC modes of operation
The mode of operation of the Unified Channel is determined by the mode select bits MODE[0:6] in the
eMIOS UC Control Register (EMIOSC[n]) (see Figure 24-15 for details).
As the internal counter EMIOSCNT[n] continues to run in all modes (except for GPIO mode), it is possible
to use this as a time base if the resource is not used in the current mode.
In order to provide smooth waveform generation even if A and B registers are changed on the fly, it is
available the MCB, OPWFMB, OPWMB and OPWMCB modes. In these modes A and B registers are
double buffered.
24.4.4.1.1.1 General purpose Input/Output (GPIO) mode
In GPIO mode, all input capture and output compare functions of the UC are disabled, the internal counter
(EMIOSCNT[n] register) is cleared and disabled. All control bits remain accessible. In order to prepare
the UC for a new operation mode, writing to registers EMIOSA[n] or EMIOSB[n] stores the same value
in registers A1/A2 or B1/B2, respectively. Writing to register EMIOSALTA[n] stores a value only in
register A2.
MODE[6] bit selects between input (MODE[6] = 0) and output (MODE[6] = 1) modes.
To Next Page
Loading...
