MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 541
24.4.3.2.7 eMIOS UC Counter Register (EMIOSCNT[n])
The EMIOSCNT[n] register contains the value of the internal counter. When GPIO mode is selected or the
channel is frozen, the EMIOSCNT[n] register is read/write. For all others modes, the EMIOSCNT[n] is a
read-only register. When entering some operation modes, this register is automatically cleared (refer to
Section 24.4.4.1.1, UC modes of operation for details).
Depending on the channel configuration it may have an internal counter or not. It means that if at least one
mode that requires the counter is implemented, then the counter is present; otherwise it is absent.
Channels of type X and G have the internal counter enabled, so their timebase can be selected by channel's
BSL[1:0]=11:eMIOS_A - channels 0 to 8, 16, 23 and 24, eMIOS_B = channels 0, 8, 16, 23 and 24. Other
channels from the above list don't have internal counters.
24.4.3.2.8 eMIOS UC Control Register (EMIOSC[n])
The Control register gathers bits reflecting the status of the UC input/output signals and the overflow
condition of the internal counter, as well as several read/write control bits.
Address: UC[n] base address + 0x08
0123456789101112131415
R0000000000000000
W
1
1
In GPIO mode or Freeze action, this register is writable.
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RC
W
1
Reset0000000000000000
Figure 24-14. eMIOS UC Counter Register (EMIOSCNT[n])
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