MPC5604B/C Microcontroller Reference Manual, Rev. 8
540 Freescale Semiconductor
24.4.3.2.6 eMIOS UC B Register (EMIOSB[n])
Depending on the mode of operation, internal registers B1 or B2 can be assigned to address EMIOSB[n].
Both B1 and B2 are cleared by reset. Table 24-16 summarizes the EMIOSB[n] writing and reading
accesses for all operation modes. For more information see Section 24.4.4.1.1, UC modes of operation.
Depending on the channel configuration, it may have EMIOSB register or not. This means that, if at least
one mode that requires the register is implemented, then the register is present; otherwise it is absent.
Address: UC[n] base address + 0x04
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
B
W
Reset0000000000000000
Figure 24-13. eMIOS UC B Register (EMIOSB[n])
Table 24-16. EMIOSA[n], EMIOSB[n] and EMIOSALTA[n] values assignment
Operation mode
Register access
write read write read alt write alt read
GPIO A1, A2 A1 B1,B2 B1 A2 A2
SAIC
1
—A2B2B2— —
SAOC
1
1
In these modes, the register EMIOSB[n] is not used, but B2 can be accessed.
A2 A1 B2 B2 — —
IPWM — A2 — B1 — —
IPM — A2 — B1 — —
DAOC A2 A1 B2 B1 — —
MC
1
A2 A1 B2 B2 — —
OPWMT A1A1B2B1A2A2
MCB
1
A2 A1 B2 B2 — —
OPWFMB A2 A1 B2 B1 — —
OPWMCB A2 A1 B2 B1 — —
OPWMB A2A1B2B1— —
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