MPC5604B/C Microcontroller Reference Manual, Rev. 8
488 Freescale Semiconductor
23.5.6 DSPI Interrupt Request Enable Register (DSPIx_RSER)
The DSPIx_RSER enables flag bits in the DSPIx_SR to generate interrupt requests.
Do not write to the DSPIx_RSER while the DSPI is running.
RFDF Receive FIFO drain flag
Indicates that the RX FIFO can be drained. Provides a method for the DSPI to request that entries
be removed from the RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be
cleared by writing ‘1’ to it, or by acknowledgement from the Edam controller when the RX FIFO is
empty.
0 RX FIFO is empty
1 RX FIFO is not empty
Note: In the interrupt service routine, RFDF must be cleared only after the DSPIx_POPR register is
read.
TXCTR TX FIFO counter
Indicates the number of valid entries in the TX FIFO. The TXCTR is incremented every time the DSPI
_PUSHR is written. The TXCTR is decremented every time an SPI command is executed and the
SPI data is transferred to the shift register.
TXNXTPTR Transmit next pointer
Indicates which TX FIFO entry is transmitted during the next transfer. The TXNXTPTR field is
updated every time SPI data is transferred from the TX FIFO to the shift register. See
Section 23.6.3.4, Transmit First In First Out (TX FIFO) buffering mechanism for more details.
RXCTR RX FIFO counter
Indicates the number of entries in the RX FIFO. The RXCTR is decremented every time the DSPI
_POPR is read. The RXCTR is incremented after the last incoming databit is sampled, but before the
t
ASC
delay starts. See Section 23.6.5.1, Classic SPI transfer format (CPHA = 0) for details.
POPNXTPT
R
Pop next pointer
Contains a pointer to the RX FIFO entry that is returned when the DSPIx_POPR is read. The
POPNXTPTR is updated when the DSPIx_POPR is read. See Section 23.6.3.5, Receive First In First
Out (RX FIFO) buffering mechanism for more details.
Table 23-18. DSPIx_SR field descriptions (continued)
Field Description
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