MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 487
Table 23-18. DSPIx_SR field descriptions
Field Description
TCF Transfer complete flag
Indicates that all bits in a frame have been shifted out. The TCF bit is set after the last incoming
databit is sampled, but before the t
ASC
delay starts. See Section 23.6.5.1, Classic SPI transfer format
(CPHA = 0) for details.
0 Transfer not complete
1 Transfer complete
TXRXS TX and RX status
Reflects the status of the DSPI. See Section 23.6.2, Start and stop of DSPI transfers for information
on what clears and sets this bit.
0 TX and RX operations are disabled (DSPI is in STOPPED state)
1 TX and RX operations are enabled (DSPI is in RUNNING state)
EOQF End of queue flag
Indicates that transmission in progress is the last entry in a queue. The EOQF bit is set when TX FIFO
entry has the EOQ bit set in the command halfword and the end of the transfer is reached. See
Section 23.6.5.1, Classic SPI transfer format (CPHA = 0) for details.
When the EOQF bit is set, the TXRXS bit is automatically cleared.
0 EOQ is not set in the executing command
1 EOQ bit is set in the executing SPI command
Note: EOQF does not function in slave mode.
TFUF Transmit FIFO underflow flag
Indicates that an underflow condition in the TX FIFO has occurred. The transmit underflow condition
is detected only for DSPI modules operating in slave mode and SPI configuration. The TFUF bit is
set when the TX FIFO of a DSPI operating in SPI slave mode is empty, and a transfer is initiated by
an external SPI master.
0 TX FIFO underflow has not occurred
1 TX FIFO underflow has occurred
TFFF Transmit FIFO fill flag
Indicates that the TX FIFO can be filled. Provides a method for the DSPI to request more entries to
be added to the TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be
cleared by writing ‘1’ to it, or an by acknowledgement from the Edam controller when the TX FIFO is
full.
0 TX FIFO is full
1 TX FIFO is not full
RFOF Receive FIFO overflow flag
Indicates that an overflow condition in the RX FIFO has occurred. The bit is set when the RX FIFO
and shift register are full and a transfer is initiated.
0 RX FIFO overflow has not occurred
1 RX FIFO overflow has occurred
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