MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 577
24.4.4.2 IP Bus Interface Unit (BIU)
The BIU provides the interface between the Internal Interface Bus (IIB) and the Peripheral Bus, allowing
communication among all submodules and this IP interface.
The BIU allows 8, 16 and 32-bit access. They are performed over a 32-bit data bus in a single cycle clock.
24.4.4.2.1 Effect of Freeze on the BIU
When the FRZ bit in the EMIOSMCR is set and the module is in debug mode, the operation of BIU is not
affected.
24.4.4.3 Global Clock Prescaler Submodule (GCP)
The GCP divides the system clock to generate a clock for the CPs of the channels. The main clock signal
is prescaled by the value defined in Figure 24-12 according to bits GPRE[0:7] in the EMIOSMCR. The
global prescaler is enabled by setting the GPREN bit in the EMIOSMCR and can be stopped at any time
by clearing this bit, thereby stopping the internal counters in all the channels.
In order to ensure safe working and avoid glitches the following steps must be performed whenever any
update in the prescaling rate is desired:
1. Write ‘0’ at GPREN bit in EMIOSMCR, thus disabling global prescaler;
2. Write the desired value for prescaling rate at GPRE[0:7] bits in EMIOSMCR;
3. Enable global prescaler by writing ‘1’ at GPREN bit in EMIOSMCR.
The prescaler is not disabled during either freeze state or negated GTBE input.
24.4.4.3.1 Effect of Freeze on the GCP
When the FRZ bit in the EMIOSMCR is set and the module is in debug mode, the operation of GCP
submodule is not affected, that is, there is no freeze function in this submodule.
24.4.5 Initialization/Application information
On resetting the eMIOS the Unified Channels enter GPIO input mode.
24.4.5.1 Considerations
Before changing an operating mode, the UC must be programmed to GPIO mode and EMIOSA[n] and
EMIOSB[n] registers must be updated with the correct values for the next operating mode. Then the
EMIOSC[n] register can be written with the new operating mode. If a UC is changed from one mode to
another without performing this procedure, the first operation cycle of the selected time base can be
random, that is, matches can occur in random time if the contents of EMIOSA[n] or EMIOSB[n] were not
updated with the correct value before the time base matches the previous contents of EMIOSA[n] or
EMIOSB[n].
When interrupts are enabled, the software must clear the FLAG bits before exiting the interrupt service
routine.
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