MPC5604B/C Microcontroller Reference Manual, Rev. 8
578 Freescale Semiconductor
24.4.5.2 Application information
Correlated output signals can be generated by all output operation modes. Bits OU[n] of the
EMIOSOUDIS register can be used to control the update of these output signals.
In order to guarantee that the internal counters of correlated channels are incremented in the same clock
cycle, the internal prescalers must be set up before enabling the global prescaler. If the internal prescalers
are set after enabling the global prescaler, the internal counters may increment in the same ratio, but at a
different clock cycle.
24.4.5.2.1 Time base generation
For MC with internal clock source operation modes, the internal counter rate can be modified by
configuring the clock prescaler ratio. Figure 24-52 shows an example of a time base with prescaler ratio
equal to one.
NOTE
MCB and OPWFMB modes have a different behavior.
Figure 24-52. Time base period when running in the fastest prescaler ratio
If the prescaler ratio is greater than one or external clock is selected, the counter may behave in three
different ways depending on the channel mode:
• If MC mode and Clear on Match Start and External Clock source are selected the internal counter
behaves as described in Figure 24-53.
• If MC mode and Clear on Match Start and Internal Clock source are selected the internal counter
behaves as described in Figure 24-54.
• If MC mode and Clear on Match End are selected the internal counter behaves as described in
Figure 24-55.
NOTE
MCB and OPWFMB modes have a different behavior.
system clock
input event/prescaler clock enable = 1
internal counter
match value = 3
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
PRE SCALED CLOCK RATIO = 1
(bypassed)
see note 1
FLAG set event
Note 1: When a match occurs, the first clock cycle is used to
clear the internal counter, starting another period.
FLAG pin/register
FLAG clear
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