Freescale Semiconductor MPC5604B - Page 590

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 579
Figure 24-53. Time base generation with external clock and clear on match start
Figure 24-54. Time base generation with internal clock and clear on match start
Figure 24-55. Time base generation with clear on match end
system clock
input event
internal counter
match value = 3
1 23
0
see note 1
Note 1: When a match occurs, the first system clock cycle is used to clear the
internal counter, and at the next edge of prescaler clock enable
1
2
the counter will start counting.
1 23
0
FLAG set event
FLAG clear
FLAG pin/register
system clock
prescaler clock enable
internal counter
match value = 3
0 13
0
2 0
3
0
PRESCALED CLOCK RATIO = 3
see note 1
Note 1: When a match occurs, the first clock cycle is used to clear the
internal counter, and only after a second edge of pre scaled clock
1
2
the counter will start counting.
FLAG set event
FLAG clear
FLAG pin/register
system clock
input event/prescaler clock enable
internal counter
match value = 3
0 13
2 0
PRESCALED CLOCK RATIO = 3
see note 1
Note 1: The match occurs only when the input event/prescaler clock enable is active.
Then, the internal counter is immediately cleared.
1
2
3
FLAG set event
FLAG clear
FLAG pin/register