Freescale Semiconductor MPC5604B - Page 553

MPC5604B/C Microcontroller Reference Manual, Rev. 8
542 Freescale Semiconductor
Address: UC[n] base address + 0x0C
0123456789101112131415
R
FREN
000
UCPRE
UCPREN
DMA
0
IF FCK FEN
0
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R00000
BSL
EDSEL
EDPOL
MODE
W
FORCMA FORCMB
Reset0000000000000000
Figure 24-15. eMIOS UC Control Register (EMIOSC[n])
Table 24-17. EMIOSC[n] field descriptions
Field Description
FREN Freeze Enable bit
The FREN bit, if set and validated by FRZ bit in EMIOSMCR register allows the channel to enter
freeze state, freezing all registers values when in debug mode and allowing the MCU to perform
debug functions.
1 = Freeze UC registers values
0 = Normal operation
UCPRE Prescaler bits
The UCPRE bits select the clock divider value for the internal prescaler of Unified Channel, as
shown in Tabl e 2 4-18.
UCPREN Prescaler Enable bit
The UCPREN bit enables the prescaler counter.
1 = Prescaler enabled
0 = Prescaler disabled (no clock)
DMA Direct Memory Access bit
The DMA bit selects if the FLAG generation will be used as an interrupt or as a CTU trigger.
1 = Flag/overrun assigned to CTU trigger
0 = Flag/overrun assigned to interrupt request
IF Input Filter
The IF field controls the programmable input filter, selecting the minimum input pulse width that can
pass through the filter, as shown in Table 2 4 -19. For output modes, these bits have no meaning.
FCK Filter Clock select bit
The FCK bit selects the clock source for the programmable input filter.
1 = Main clock
0 = Prescaled clock