MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 543
FEN FLAG Enable bit
The FEN bit allows the Unified Channel FLAG bit to generate an interrupt signal or a CTU trigger
signal (The type of signal to be generated is defined by the DMA bit).
1 = Enable (FLAG will generate an interrupt request or a CTU trigger)
0 = Disable (FLAG does not generate an interrupt request or a CTU trigger)
FORCMA Force Match A bit
For output modes, the FORCMA bit is equivalent to a successful comparison on comparator A
(except that the FLAG bit is not set). This bit is cleared by reset and is always read as zero. This bit
is valid for every output operation mode which uses comparator A, otherwise it has no effect.
1 = Force a match at comparator A
0 = Has no effect
Note: For input modes, the FORCMA bit is not used and writing to it has no effect.
FORCMB Force Match B bit
For output modes, the FORCMB bit is equivalent to a successful comparison on comparator B
(except that the FLAG bit is not set). This bit is cleared by reset and is always read as zero. This bit
is valid for every output operation mode which uses comparator B, otherwise it has no effect.
1 = Force a match at comparator B
0 = Has not effect
Note: For input modes, the FORCMB bit is not used and writing to it has no effect.
BSL Bus Select
The BSL field is used to select either one of the counter buses or the internal counter to be used by
the Unified Channel. Refer to Table 24-20 for details.
EDSEL Edge Selection bit
For input modes, the EDSEL bit selects whether the internal counter is triggered by both edges of a
pulse or just by a single edge as defined by the EDPOL bit. When not shown in the mode of
operation description, this bit has no effect.
1 = Both edges triggering
0 = Single edge triggering defined by the EDPOL bit
For GPIO in mode, the EDSEL bit selects if a FLAG can be generated.
1 = No FLAG is generated
0 = A FLAG is generated as defined by the EDPOL bit
For SAOC mode, the EDSEL bit selects the behavior of the output flip-flop at each match.
1 = The output flip-flop is toggled
0 = The EDPOL value is transferred to the output flip-flop
EDPOL Edge Polarity bit
For input modes, the EDPOL bit asserts which edge triggers either the internal counter or an input
capture or a FLAG. When not shown in the mode of operation description, this bit has no effect.
1 = Trigger on a rising edge
0 = Trigger on a falling edge
For output modes, the EDPOL bit is used to select the logic level on the output pin.
1 = A match on comparator A sets the output flip-flop, while a match on comparator B clears it
0 = A match on comparator A clears the output flip-flop, while a match on comparator B sets it
MODE Mode selection
The MODE field selects the mode of operation of the Unified Channel, as shown in Table 24-21.
Note: If a reserved value is written to mode the results are unpredictable.
Table 24-17. EMIOSC[n] field descriptions (continued)
Field Description
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