MPC5604B/C Microcontroller Reference Manual, Rev. 8
546 Freescale Semiconductor
24.4.3.2.10 eMIOS UC Alternate A Register (EMIOSALTA[n])
The EMIOSALTA[n] register provides an alternate address to access A2 channel registers in restricted
modes (GPIO, OPWMT) only. If EMIOSA[n] register is used along with EMIOSALTA[n], both A1 and
A2 registers can be accessed in these modes. Figure 24-16 summarizes the EMIOSALTA[n] writing and
reading accesses for all operation modes. Please, see Section 24.4.4.1.1.1, General purpose Input/Output
(GPIO) mode, Section 24.4.4.1.1.12, Output Pulse Width Modulation with Trigger (OPWMT) mode for a
more detailed description of the use of EMIOSALTA[n] register.
Table 24-22. EMIOSS[n] field descriptions
Field Description
OVR Overrun bit
The OVR bit indicates that FLAG generation occurred when the FLAG bit was already set.
1 = Overrun has occurred
0 = Overrun has not occurred
OVFL Overflow bit
The OVFL bit indicates that an overflow has occurred in the internal counter. OVFL must be cleared
by software writing a 1 to the OVFLC bit.
1 = An overflow had occurred
0 = No overflow
UCIN Unified Channel Input pin bit
The UCIN bit reflects the input pin state after being filtered and synchronized.
UCOUT UCOUT — Unified Channel Output pin bit
The UCOUT bit reflects the output pin state.
FLAG FLAG bit
The FLAG bit is set when an input capture or a match event in the comparators occurred.
1 = FLAG set event has occurred
0 = FLAG cleared
Note: When DMA bit is set, the FLAG bit can be cleared by the CTU.
Address: UC[n] base address + 0x14
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ALTA
W
Reset0000000000000000
Figure 24-17. eMIOS UC Alternate A register (EMIOSALTA[n])
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