MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 729
address is incremented to the next-higher 16-byte boundary, and a flash memory array prefetch is initiated
if the data is not already resident in a page buffer. Prefetched data is always loaded into the
least-recently-used buffer.
Buffers may be in one of six states, listed here in order of priority:
1. Invalid — The buffer contains no valid data.
2. Used — The buffer contains valid data which has been provided to satisfy an AHB burst type read.
3. Valid — The buffer contains valid data which has been provided to satisfy an AHB single type
read.
4. Prefetched — The buffer contains valid data which has been prefetched to satisfy a potential future
AHB access.
5. Busy AHB — The buffer is currently being used to satisfy an AHB burst read.
6. Busy Fill — The buffer has been allocated to receive data from the flash memory array, and the
array access is still in progress.
Selection of a buffer to be loaded on a miss is based on the following replacement algorithm:
1. First, the buffers are examined to determine if there are any invalid buffers. If there are multiple
invalid buffers, the one to be used is selected using a simple numeric priority, where buffer 0 is
selected first, then buffer 1, etc.
2. If there are no invalid buffers, the least-recently-used buffer is selected for replacement.
Once the candidate page buffer has been selected, the flash memory array is accessed and read data loaded
into the buffer. If the buffer load was in response to a miss, the just-loaded buffer is immediately marked
as most-recently-used. If the buffer load was in response to a speculative fetch to the next-sequential line
address after a buffer hit, the recently-used status is not changed. Rather, it is marked as most-recently-used
only after a subsequent buffer hit.
This policy maximizes performance based on reference patterns of flash memory accesses and allows for
prefetched data to remain valid when non-prefetch enabled bus masters are granted flash memory access.
Several algorithms are available for prefetch control which trade off performance versus power. They are
defined by the Bx_Py_PFLM (prefetch limit) register field. More aggressive prefetching increases power
slightly due to the number of wasted (discarded) prefetches, but may increase performance by lowering
average read latency.
In order for prefetching to occur, a number of control bits must be enabled. Specifically, the global buffer
enable (PFCRn[Bx_Py_BFE]) must be set, the prefetch limit (PFCRn[Bx_Py_PFLM]) must be non-zero,
either instruction prefetching (PFCRn[Bx_Py_IPFE]) or data prefetching (PFCRn[Bx_Py_DPFE])
enabled, and Master Access must be enabled (PFAPR[MxPFD]). See Section 27.7.2.2, Register
description, for a description of these control fields.
27.8.8.1 Instruction/Data prefetch triggering
Prefetch triggering may be enabled for instruction reads via the Bx_Py_IPFE control field, while
prefetching for data reads is enabled via the Bx_Py_DPFE control field. Additionally, the Bx_Py_PFLIM
field must be set to enable prefetching. Prefetches are never triggered by write cycles.
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