MPC5604B/C Microcontroller Reference Manual, Rev. 8
168 Freescale Semiconductor
• from RUN0…3, SAFE, or TEST mode when the TARGET_MODE bit field of the ME_MCTL
register is written with “0011”
• from the STANDBY mode after an external wakeup event or internal wakeup alarm (e.g. RTC/API
event)
As soon as any of the above events has occurred, a DRUN mode transition request is generated. The mode
configuration information for this mode is provided by the ME_DRUN_MC register. In this mode, the
flashes, all clock sources, and the system clock configuration can be controlled by software as required.
After system reset, the software execution starts with the default configuration selecting the 16 MHz int.
RC osc. as the system clock.
This mode is intended to be used by software
• to initialize all registers as per the system needs
• to execute small routines in a ‘ping-pong’ with the STANDBY mode
When this mode is entered from STANDBY after a wakeup event, the ME_DRUN_MC register content
is restored to its pre-STANDBY values, and the mode starts in that configuration.
All power domains are active when this mode is entered due to a system reset sequence initiated by a
destructive reset event. In other cases of entry, such as the exit from STANDBY after a wakeup event, a
functional reset event like an external reset or a software request from RUN0…3, SAFE, or TEST mode,
active power domains are determined by the power configuration register PCU_PCONF2 of the MC_PCU.
All power domains except power domains #0 and #1 are configurable in this mode (see the MC_PCU
chapter for details).
NOTE
As flashes can be configured in low-power or power-down state in this
mode, software must ensure that the code executes from SRAM before
changing to this mode.
8.4.2.3 SAFE Mode
The device enters this mode on the following events:
• from DRUN, RUN0…3, or TEST mode when the TARGET_MODE bit field of the ME_MCTL
register is written with “0010”
• from any mode except RESET due to a SAFE mode request generated by the MC_RGM because
of some potentially recoverable hardware failure in the system (see the MC_RGM chapter for
details)
As soon as any of the above events has occurred, a SAFE mode transition request is generated. The mode
configuration information for this mode is provided by the ME_SAFE_MC register. This mode has a
pre-defined configuration, and the 16 MHz int. RC osc. is selected as the system clock. All power domains
are made active in this mode.
If the SAFE mode is requested by software while some other mode transition process is ongoing, the new
target mode becomes the SAFE mode regardless of other pending requests. In this case, the new mode
request is not interpreted as an invalid request.
To Next Page
