MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 169
NOTE
If software requests to change to the SAFE mode and then requests to
change back to the parent mode before the mode transition is completed, the
device’s final mode after mode transition will be the parent mode. However,
this is not recommended software behavior. It is recommended for software
to wait until the S_MTRANS bit is cleared after requesting a change to
SAFE before requesting another mode change.
As long as a SAFE event is active, the system remains in the SAFE mode and no write access is allowed
to the ME_MCTL register.
This mode is intended to be used by software
• to assess the severity of the cause of failure and then to either
— re-initialize the device via the DRUN mode, or
— completely reset the device via the RESET mode.
If the outputs of the system I/Os need to be forced to a high impedance state upon entering this mode, the
PDO bit of the ME_SAFE_MC register should be set. In this case, the pads’ power sequence driver cell is
also disabled. The input levels remain unchanged.
8.4.2.4 TEST Mode
The device enters this mode on the following events:
• from the DRUN mode when the TARGET_MODE bit field of the ME_MCTL register is written
with “0001”
As soon as any of the above events has occurred, a TEST mode transition request is generated. The mode
configuration information for this mode is provided by the ME_TEST_MC register. Except for the main
voltage regulator, all resources of the system are configurable in this mode. The system clock to the whole
system can be stopped by programming the SYSCLK bit field to “1111”, and in this case, the only way to
exit this mode is via a device reset.
This mode is intended to be used by software
• to execute on-chip test routines
All power domains except power domains #0 and #1 are configurable in this mode. Active power domains
are determined by the power configuration register PCU_PCONF2 of the MC_PCU.
NOTE
As flash modules can be configured to a low-power or power-down state in
these modes, software must ensure that the code will execute from SRAM
before it changes to this mode.
8.4.2.5 RUN0…3 Modes
The device enters one of these modes on the following events:
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