MPC5604B/C Microcontroller Reference Manual, Rev. 8
170 Freescale Semiconductor
• from the DRUN another RUN0…3 mode when the TARGET_MODE bit field of the ME_MCTL
register is written with “0100…0111”
• from the HALT mode by an interrupt event
• from the STOP mode by an interrupt or wakeup event
As soon as any of the above events occur, a RUN0…3 mode transition request is generated. The mode
configuration information for these modes is provided by ME_RUN0…3_MC registers. In these modes,
the flashes, all clock sources, and the system clock configuration can be controlled by software as required.
These modes are intended to be used by software
• to execute application routines
All power domains except power domains #0 and #1 are configurable in these modes in order to reduce
leakage consumption. Active power domains are determined by the power configuration register
PCU_PCONF2 of the MC_PCU.
NOTE
As flash modules can be configured to a low-power or power-down state in
these modes, software must ensure that the code will execute from SRAM
before it changes to this mode.
8.4.2.6 HALT Mode
The device enters this mode on the following events:
• from one of the RUN0…3 modes when the TARGET_MODE bit field of the ME_MCTL register
is written with “1000”.
As soon as any of the above events occur, a HALT mode transition request is generated. The mode
configuration information for this mode is provided by ME_HALT_MC register. This mode is quite
configurable, and the ME_HALT_MC register should be programmed according to the system needs. The
main voltage regulator and the flashes can be put in power-down mode as needed. If there is a HALT mode
request while an interrupt request is active, the device mode does not change, and an invalid mode interrupt
is not generated.
This mode is intended as a first level low-power mode with
• the core clock frozen
• only a few peripherals running
and to be used by software
• to wait until it is required to do something and then to react quickly (i.e. within a few system clock
cycles of an interrupt event)
All power domains except power domains #0 and #1 are configurable in this mode in order to reduce
leakage consumption. Active power domains are determined by the power configuration register
PCU_PCONF2 of the MC_PCU.
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