MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 533
— Both eMIOS blocks can be synchronized
• One global prescaler
• 16-bit data registers
• 10 x 16-bit wide counter buses
— Counter buses B, C, D, and E can be driven by Unified Channel 0, 8, 16, and 24, respectively
— Counter bus A is driven by the Unified Channel #23
— Several channels have their own time base, alternative to the counter buses
— Shared timebases through the counter buses
— Synchronization among timebases
• Control and Status bits grouped in a single register
• Shadow FLAG register
• State of the UC can be frozen for debug purposes
• Motor control capability
24.4.1.3 Modes of operation
The Unified Channels can be configured to operate in the following modes:
• General purpose input/output
• Single Action Input Capture
• Single Action Output Compare
• Input Pulse Width Measurement
• Input Period Measurement
• Double Action Output Compare
• Modulus Counter
• Modulus Counter Buffered
• Output Pulse Width and Frequency Modulation Buffered
• Output Pulse Width Modulation Buffered
• Output Pulse Width Modulation with Trigger
• Center Aligned Output Pulse Width Modulation Buffered
These modes are described in Section 24.4.4.1.1, UC modes of operation.
Each channel can have a specific set of modes implemented, according to device requirements.
If an unimplemented mode (reserved) is selected, the results are unpredictable such as writing a reserved
value to MODE[0:6] in Section 24.4.3.2.8, eMIOS UC Control Register (EMIOSC[n]).
24.4.1.4 Channel implementation
Figure 24-7 shows the channel configuration of the eMIOS blocks.
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