MPC5604B/C Microcontroller Reference Manual, Rev. 8
716 Freescale Semiconductor
Throughout this document, several important terms are used to describe the platform flash memory
controller module and its connections. These terms are defined here:
• Port — This is used to describe the AMBA-AHB connection(s) into the platform flash memory
controller. From an architectural and programming model viewpoint, the definition supports up to
two AHB ports, even though this specific controller only supports a single AHB connection.
• Bank — This term is used to describe the attached flash memories. From the platform flash
memory controller’s perspective, there may be one or two attached banks of flash memory. The
“code flash memory” is required and always attached to bank0. Additionally, there is a “data flash
memory” attached to bank1. The platform flash memory controller interface supports two separate
connections, one to each memory bank.
• Array — Within each memory bank, there is one flash memory array instantiations.
• Page — This value defines the number of bits read from the flash memory array in a single access.
For this controller and memory, the page size is 128 bits (16 bytes).
The nomenclature “page buffers and “line buffers” are used interchangeably.
27.7.1.1 Overview
The platform flash memory controller supports a 32-bit data bus width at the AHB port and connections
to 128-bit read data interfaces from two memory banks, where each bank contains one instantiations of the
flash memory array. One flash memory bank is connected to the code flash memory and the other bank is
connected to the optional data flash memory. The memory controller capabilities vary between the two
banks with each bank’s functionality optimized with the typical use cases associated with the attached
flash memory. As an example, the platform flash memory controller logic associated with the code flash
memory bank contains a four-entry “page” buffer, each entry containing 128 bits of data (1 flash memory
page) plus an associated controller which prefetches sequential lines of data from the flash memory array
into the buffer, while the controller logic associated with the data flash memory bank only supports a
128-bit register which serves as a temporary page holding register and does not support any prefetching.
Prefetch buffer hits from the code flash memory bank support zero-wait AHB data phase responses. AHB
read requests which miss the buffers generate the needed flash memory array access and are forwarded to
the AHB upon completion, typically incurring two wait-states at an operating frequency of 60–64 MHz.
This memory controller is optimized for applications where a cacheless processor core, e.g., the Power
e200z0h, is connected through the platform to on-chip memories, e.g., flash memory and SRAM, where
the processor and platform operate at the same frequency. For these applications, the 2-stage pipeline
AMBA-AHB system bus is effectively mapped directly into stages of the processor’s pipeline and zero
wait-state responses for most memory accesses are critical for providing the required level of system
performance.
27.7.1.2 Features
The following list summarizes the key features of the platform flash memory controller:
• Dual array interfaces support up to a total of 16 MB of flash memory, partitioned as two separate
8 MB banks
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