MPC5604B/C Microcontroller Reference Manual, Rev. 8
476 Freescale Semiconductor
DCONF DSPI configuration
The following table lists the DCONF values for the various configurations.
FRZ Freeze
Enables the DSPI transfers to be stopped on the next frame boundary when the device enters
debug mode.
0 Do not halt serial transfers
1 Halt serial transfers
MTFE Modified timing format enable
Enables a modified transfer format to be used. See Section 23.6.5.4, Modified SPI transfer
format (MTFE = 1, CPHA = 1), for more information.
0 Modified SPI transfer format disabled
1 Modified SPI transfer format enabled
PCSSE Peripheral chip select strobe enable
Enables the CS5_x to operate as a CS strobe output signal.
See Section 23.6.4.5, Peripheral chip select strobe enable (CS5_x), for more information.
0CS5_x is used as the Peripheral chip select 5 signal
1CS5_x as an active-low CS strobe signal
ROOE Receive FIFO overflow overwrite enable
Enables an RX FIFO overflow condition to ignore the incoming serial data or to overwrite
existing data. If the RX FIFO is full and new data is received, the data from the transfer that
generated the overflow is ignored or put in the shift register.
If the ROOE bit is set, the incoming data is put in the shift register. If the ROOE bit is cleared,
the incoming data is ignored. See Section 23.6.7.6, Receive FIFO Overflow Interrupt Request
(RFOF), for more information.
0 Incoming data is ignored
1 Incoming data is put in the shift register
PCSISn Peripheral chip select inactive state
Determines the inactive state of the CS0_x signal. CS0_x must be configured as inactive high
for slave mode operation.
0 The inactive state of CS0_x is low
1 The inactive state of CS0_x is high
Table 23-3. DSPIx_MCR field descriptions (continued)
Field Description
DCONF Configuration
00 SPI
01 Invalid value
10 Invalid value
11 Invalid value
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