Freescale Semiconductor MPC5604B - Page 488

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 477
MDIS Module disable
Allows the clock to stop to the non-memory mapped logic in the DSPI, effectively putting the
DSPI in a software controlled power-saving state. See Section 23.6.8, Power saving features
for more information.
0 Enable DSPI clocks
1 Allow external logic to disable DSPI clocks
DIS_TXF Disable transmit FIFO
Enables and disables the TX FIFO. When the TX FIFO is disabled, the transmit part of the DSPI
operates as a simplified double-buffered SPI. See Section 23.6.3.3, FIFO disable operation for
details.
0 TX FIFO is enabled
1 TX FIFO is disabled
DIS_RXF Disable receive FIFO
Enables and disables the RX FIFO. When the RX FIFO is disabled, the receive part of the DSPI
operates as a simplified double-buffered SPI. See Section 23.6.3.3, FIFO disable operation for
details.
0 RX FIFO is enabled
1 RX FIFO is disabled
CLR_TXF Clear TX FIFO. CLR_TXF is used to flush the TX FIFO. Writing a ‘1’ to CLR_TXF clears the TX
FIFO Counter. The CLR_TXF bit is always read as zero.
0 Do not clear the TX FIFO Counter
1 Clear the TX FIFO Counter
CLR_RXF Clear RX FIFO. CLR_RXF is used to flush the RX FIFO. Writing a ‘1’ to CLR_RXF clears the
RX Counter. The CLR_RXF bit is always read as zero.
0 Do not clear the RX FIFO Counter
1 Clear the RX FIFO Counter
SMPL_PT Sample point
Allows the host software to select when the DSPI master samples SIN in modified transfer
format. Figure 23-18 shows where the master can sample the SIN pin. The following table lists
the delayed sample points.
HALT Halt
Provides a mechanism for software to start and stop DSPI transfers. See Section 23.6.2, Start
and stop of DSPI transfers, for details on the operation of this bit.
0 Start transfers
1 Stop transfers
Table 23-3. DSPIx_MCR field descriptions (continued)
Field Description
SMPL_PT
Number of system clock cycles between
odd-numbered edge of SCK_x and sampling of SIN_x
00 0
01 1
10 2
11 Reserved