MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 113
• SXOSC_clk: clock coming from the slow external crystal oscillator
• SIRC_clk: clock coming from the slow (low frequency) internal RC oscillator
• FIRC_clk: clock coming from the fast (high frequency) internal RC oscillator
• FMPLL_clk: clock coming from the FMPLL
•f
FXOSC_clk:
frequency of fast external crystal oscillator clock
•f
SXOSC_clk
: frequency of slow external crystal oscillator clock
•f
SIRC_clk
: frequency of slow (low frequency) internal RC oscillator
•f
FIRC_clk
: frequency of fast (high frequency) internal RC oscillator
•f
FMPLL_clk
: frequency of FMPLL clock
6.8.4.1 Crystal clock monitor
If f
FXOSC_clk
is less than f
FIRC_clk
divided by 2
RCDIV
bits of the CMU_CSR and the FXOSC_clk is ‘ON’ as
signalled by the MC_ME then:
• An event pending bit OLRI in CMU_ISR is set.
• A failure event OLR is signalled to the MC_RGM which in turn can automatically switch to a safe
fallback clock and generate an interrupt or reset.
6.8.4.2 FMPLL clock monitor
The f
FMPLL_clk
can be monitored by programming bit CME of the CMU_CSR register to ‘1’. The
FMPLL_clk monitor starts as soon as bit CME is set. This monitor can be disabled at any time by writing
bit CME to ‘0’.
If f
FMPLL_clk
is greater than a reference value determined by bits HFREF[11:0] of the CMU_HFREFR and
the FMPLL_clk is ‘ON’, as signalled by the MC_ME, then:
• An event pending bit FHHI in CMU_ISR is set.
• A failure event is signalled to the MC_RGM which in turn can generate an interrupt or safe mode
request or functional reset depending on the programming model.
If f
FMPLL_clk
is less than a reference value determined by bits LFREF[11:0] of the CMU_LFREFR and the
FMPLL_clk is ‘ON’, as signaled by the MC_ME, then:
• An event pending bit FLLI in CMU_ISR is set.
• A failure event FLL is signalled to the MC_RGM which in turn can generate an interrupt or safe
mode request or functional reset depending on the programming model.
NOTE
The internal RC oscillator is used as reliable reference clock for the clock
supervision. In order to avoid false events, proper programming of the
dividers is required. These have to take into account the accuracy and
frequency deviation of the internal RC oscillator.
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