MPC5604B/C Microcontroller Reference Manual, Rev. 8
180 Freescale Semiconductor
• all the updated status bits in the ME_GS register match the configuration specified in the
ME_<target mode>_MC register
• power sequences are done
• clock disable/enable process is finished
• processor low-power mode (halt/stop) entry and exit processes are finished
Software can monitor the mode transition status by reading the S_MTRANS bit of the ME_GS register.
The mode transition latency can differ from one mode to another depending on the resources’ availability
before the new mode request and the target mode’s requirements.
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