MPC5604B/C Microcontroller Reference Manual, Rev. 8
292 Freescale Semiconductor
of the preempted context, the processor will return to the instruction address that it was to next execute
before it was preempted. This next instruction is part of the preempted ISR or the interrupt exception
handler’s prolog or epilog.
Figure 16-11. Software vector mode handshaking timing diagram
16.6.3.2 Hardware vector mode handshaking
A timing diagram of the interrupt request and acknowledge handshaking in hardware vector mode, along
with the handshaking near the end of the interrupt exception handler, is shown in Figure 16-12. As in
software vector mode, the INTC examines the peripheral and software settable interrupt requests, and
when it finds an asserted one with a higher priority than PRI in INTC_CPR, it asserts the interrupt request
to the processor. The INTVEC field in the INTC_IACKR is updated with the preempting peripheral or
software settable interrupt request’s vector when the interrupt request to the processor is asserted. The
INTVEC field retains that value until the next time the interrupt request to the processor is asserted. In
addition, the value of the interrupt vector to the processor matches the value of the INTVEC field in the
INTC_IACKR. The rest of the handshaking is described in Section 16.7.2.2, “Hardware vector mode.
The handshaking near the end of the interrupt exception handler, that is the writing to the INTC_EOIR, is
the same as in software vector mode. Refer to Section 16.6.3.1.2, “End of interrupt exception handler.
010
Clock
Interrupt request to processor
Hardware vector enable
Interrupt vector
Interrupt acknowledge
Read INTC_IACKR
Write INTC_EOIR
INTVEC in INTC_IACKR
PRI in INTC_CPR
Peripheral interrupt request 100
0 108
0
To Next Page
Loading...
