MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 325
bit, so if this approach is followed, there are no coherency issues associated with the multi-cycle
descriptor writes. Deletion/removal of an existing memory region is performed simply by clearing
MPU_RGDn.Word3[VLD].
2. If only the access rights for an existing region descriptor need to change, a 32-bit write to the
alternate version of the access control word (MPU_RGDAACn) would typically be performed.
Recall writes to the region descriptor using this alternate access control location do not affect the
valid bit, so there are, by definition, no coherency issues involved with the update. The access
rights associated with the memory region switch instantaneously to the new value as the IPS write
completes.
3. If the region’s start and end addresses are to be changed, this would typically be performed by
writing a minimum of three words of the region descriptor: MPU_RGDn.Word{0,1,3}, where the
writes to Word0 and Word1 redefine the start and end addresses respectively and the write to
Word3 re-enables the region descriptor valid bit. In many situations, all four words of the region
descriptor would be rewritten.
4. Typically, references to the MPU’s programming model would be restricted to supervisor mode
accesses from a specific processor(s), so a region descriptor would be specifically allocated for this
purpose with attempted accesses from other masters or while in user mode terminated with an error.
When the MPU detects an access error, the current bus cycle is terminated with an error response and
information on the faulting reference captured in the MPU_EARn and MPU_EDRn registers. The
error-terminated bus cycle typically initiates some type of error response in the originating bus master. For
example, the CPU errors will generate a core exception, whereas the DMA errors will generate a MPU
(external) interrupt. It is important to highlight that in case of DMA access violations the core will continue
to run, but if a core violation occurs the system will stop. In any event, the processor can retrieve the
captured error address and detail information simply be reading the MPU_E{A,D}Rn registers.
Information on which error registers contain captured fault data is signaled by MPU_CESR[SPERR].
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