MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 415
21.8.2.2.7 Valid message
A received or transmitted message is considered as valid when the data has been received or transmitted
without error according to the LIN protocol.
21.8.2.2.8 Overrun
Once the message buffer is full, the next valid message reception leads to an overrun and a message is lost.
The hardware sets the BOF bit in the LINSR to signal the overrun condition. Which message is lost
depends on the configuration of the RX message buffer:
• If the buffer lock function is disabled (LINCR1[RBLM] = 0) the last message stored in the buffer
is overwritten by the new incoming message. In this case the latest message is always available to
the application.
• If the buffer lock function is enabled (LINCR1[RBLM] = 0) the most recent message is discarded
and the previous message is available in the buffer.
21.8.2.3 Slave mode with identifier filtering
In the LIN protocol the identifier of a message is not associated with the address of a node but related to
the content of the message. Consequently a transmitter broadcasts its message to all receivers. On header
reception a slave node decides—depending on the identifier value—whether the software needs to receive
or send a response. If the message does not target the node, it must be discarded without software
intervention.
To fulfill this requirement, the LINFlex controller provides configurable filters in order to request software
intervention only if needed. This hardware filtering saves CPU resources that would otherwise be needed
by software for filtering.
21.8.2.3.1 Filter mode
Usually each of the eight IFCR registers filters one dedicated identifier, but this limits the number of
identifiers LINFlex can handle to the number of IFCR registers implemented in the device. Therefore, in
order to be able to handle more identifiers, the filters can be configured in mask mode.
In identifier list mode (the default mode), both filter registers are used as identifier registers. All bits of
the incoming identifier must match the bits specified in the filter register.
In mask mode, the identifier registers are associated with mask registers specifying which bits of the
identifier are handled as “must match” or as “don’t care”. For the bit mapping and registers organization,
please see Figure 21-29.
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