MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 473
23.4.2.2 Peripheral Chip Selects 1–3 (CS1:3_x)
CS1:3_x are peripheral chip select output signals in master mode. In slave mode these signals are not used.
23.4.2.3 Peripheral Chip Select 4 (CS4_x)
CS4_x is a peripheral chip select output signal in master mode.
23.4.2.4 Peripheral Chip Select 5 / Peripheral Chip Select Strobe
(CS5_x)
CS5_x is a peripheral chip select output signal. When the DSPI is in master mode and PCSSE bit in the
DSPIx_MCR is cleared, the CS5_x signal is used to select the slave device that receives the current
transfer.
CS5_x is a strobe signal used by external logic for deglitching of the CS signals. When the DSPI is in
master mode and the PCSSE bit in the DSPIx_MCR is set, the CS5_x signal indicates the timing to decode
CS0:4_x signals, which prevents glitches from occurring.
CS5_x is not used in slave mode.
23.4.2.5 Serial Input (SIN_x)
SIN_x is a serial data input signal.
23.4.2.6 Serial Output (SOUT_x)
SOUT_x is a serial data output signal.
23.4.2.7 Serial Clock (SCK_x)
SCK_x is a serial communication clock signal. In master mode, the DSPI generates the SCK. In slave
mode, SCK_x is an input from an external bus master.
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