Freescale Semiconductor MPC5604B - Page 620

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 609
25.4.2.2 Main Status Register (MSR)
The Main Status Register (MSR) provides status bits for the ADC.
CTUEN Cross trigger unit conversion enable
0 CTU triggered conversion disabled
1 CTU triggered conversion enabled
ADCLKSEL Analog clock select
This bit can only be written when ADC in Power-Down mode
0 ADC clock frequency is half Peripheral Set Clock frequency
1 ADC clock frequency is equal to Peripheral Set Clock frequency
ABORTCHAI
N
Abort Chain
When this bit is set, the ongoing Chain Conversion is aborted. This bit is reset by hardware as soon
as a new conversion is requested.
0 Conversion is not affected
1 Aborts the ongoing chain conversion
ABORT Abort Conversion
When this bit is set, the ongoing conversion is aborted and a new conversion is invoked. This bit is
reset by hardware as soon as a new conversion is invoked. If it is set during a scan chain, only the
ongoing conversion is aborted and the next conversion is performed as planned.
0 Conversion is not affected
1 Aborts the ongoing conversion
ACKO Auto-clock-off enable
If set, this bit enables the Auto clock off feature.
0 Auto clock off disabled
1 Auto clock off enabled
PWDN Power-down enable
When this bit is set, the analog module is requested to enter Power Down mode. When ADC status
is PWDN, resetting this bit starts ADC transition to IDLE mode.
0 ADC is in normal mode
1 ADC has been requested to power down
Table 25-7. MCR field descriptions (continued)
Field Description