Freescale Semiconductor MPC5604B - Page 670

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 659
27.5.1.3 CFlash Secondary Low/Mid Address Space Block Locking Register
(CFLASH_SLL)
The CFlash Secondary Low/Mid Address Space Block Locking Register provides an alternative means to
protect blocks from being modified. These bits, along with bits in the CFLASH_LML register, determine
if the block is locked from Program or Erase. An “OR” of CFLASH_LML and CFLASH_SLL determine
the final lock status.
MLK Mid address space block LocK
These bits are used to lock the blocks of Mid Address Space from Program and Erase.
MLK[1:0] are related to sectors B0F7-6, respectively.
A value of 1 in a bit of the MLK register signifies that the corresponding block is locked for
Program and Erase.
A value of 0 in a bit of the MLK register signifies that the corresponding block is available to
receive program and erase pulses.
The MLK register is not writable once an interlock write is completed until
CFLASH_MCR[DONE] is set at the completion of the requested operation. Likewise, the
MLK register is not writable if a high voltage operation is suspended.
Upon reset, information from the TestFlash block is loaded into the MLK registers. The MLK
bits may be written as a register. Reset will cause the bits to go back to their TestFlash block
value. The default value of the MLK bits (assuming erased fuses) would be locked.
In the event that blocks are not present (due to configuration or total memory size), the MLK
bits will default to locked, and will not be writable. The reset value will always be 1
(independent of the TestFlash block), and register writes will have no effect.
MLK is not writable unless LME is high.
0: Mid Address Space Block is unlocked and can be modified (also if CFLASH_SLL[SMLK]
= 0).
1: Mid Address Space Block is locked and cannot be modified.
LLK Low address space block LocK
These bits are used to lock the blocks of Low Address Space from Program and Erase.
LLK[5:0] are related to sectors B0F5-0, respectively. LLK[15:6] are not used for this memory
cut.
A value of 1 in a bit of the LLK register signifies that the corresponding block is locked for
Program and Erase.
A value of 0 in a bit of the LLK register signifies that the corresponding block is available to
receive program and erase pulses.
The LLK register is not writable once an interlock write is completed until
CFLASH_MCR[DONE] is set at the completion of the requested operation. Likewise, the
LLK register is not writable if a high voltage operation is suspended.
Upon reset, information from the TestFlash block is loaded into the LLK registers. The LLK
bits may be written as a register. Reset will cause the bits to go back to their TestFlash block
value. The default value of the LLK bits (assuming erased fuses) would be locked.
In the event that blocks are not present (due to configuration or total memory size), the LLK
bits will default to locked, and will not be writable. The reset value will always be 1
(independent of the TestFlash block), and register writes will have no effect.
Bits LLK[15:6] are read-only and locked at ‘1’.
LLK is not writable unless LME is high.
0: Low Address Space Block is unlocked and can be modified (also if CFLASH_SLL[SLK] =
0).
1: Low Address Space Block is locked and cannot be modified.
Table 27-15. CFLASH_NVLML field descriptions (continued)
Field Description