Freescale Semiconductor MPC5604B - Page 702

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 691
27.5.2.3.1 DFlash Nonvolatile Secondary Low/Mid Address Space Block Locking
Register (DFLASH_NVSLL)
The DFLASH_SLL register has a related Nonvolatile Secondary Low/Mid Address Space Block Locking
register located in TestFlash that contains the default reset value for DFLASH_SLL. During the reset phase
of the flash memory module, the DFLASH_NVSLL register content is read and loaded into the
DFLASH_SLL.
The DFLASH_NVSLL register is a 64-bit register, of which the 32 most significant bits 63:32 are ‘don’t
care’ and are used to manage ECC codes.
Offset: 0xC03DF8 Access: Read/write
0123456789101112131415
R
SLE1111111111
STSLK
1111
W
Reset
1111111111111111
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
111111111111
SLK
W
Reset
1111111111111111
Figure 27-27. DFlash Nonvolatile Secondary Low/mid address space block Locking register
(DFLASH_NVSLL)