MPC5604B/C Microcontroller Reference Manual, Rev. 8
696 Freescale Semiconductor
MRE Margin Read Enable
MRE enables margin reads to be done. This bit, combined with MRV, enables regular user mode reads
to be replaced by margin reads.
Margin reads are only active during Array Integrity Checks; Normal User reads are not affected by MRE.
This bit is not accessible whenever DFLASH_MCR[DONE] or DFLASH_UT0[AID] are low: reading
returns indeterminate data
while writing has no effect.
0: Margin reads are not enabled, all reads are User mode reads.
1: Margin reads are enabled.
MRV Margin Read Value
If MRE is high, MRV selects the margin level that is being checked. Margin can be checked to an erased
level (MRV = 1) or to a programmed level (MRV = 0).
This bit is not accessible whenever DFLASH_MCR[DONE] or DFLASH_UT0[AID] are low: reading
returns indeterminate data while writing has no effect.
0: Zero’s (programmed) margin reads are requested (if MRE = 1).
1: One’s (erased) margin reads are requested (if MRE = 1).
EIE ECC data Input Enable
EIE enables the ECC Logic Check operation to be done.
This bit is not accessible whenever DFLASH_MCR[DONE] or DFLASH_UT0[AID] are low: reading
returns indeterminate data while writing has no effect.
0: ECC Logic Check is not enabled.
1: ECC Logic Check is enabled.
AIS Array Integrity Sequence
AIS determines the address sequence to be used during array integrity checks or Margin Read.
The default sequence (AIS = 0) is meant to replicate sequences normal user code follows, and
thoroughly checks the read propagation paths. This sequence is proprietary.
The alternative sequence (AIS = 1) is just logically sequential. Proprietary sequence is forbidden in
Margin Read.
It should be noted that the time to run a sequential sequence is significantly shorter than the time to run
the proprietary sequence.
This bit is not accessible whenever DFLASH_MCR[DONE] or DFLASH_UT0[AID] are low: reading
returns indeterminate data while writing has no effect.
0: Array Integrity equence is proprietary sequence.
1: Array Integrity or Margin Read sequence is sequential.
AIE Array Integrity Enable
AIE set to ‘1’ starts the Array Integrity Check done on all selected and unlocked blocks.
The pattern is selected by AIS, and the MISR (DFLASH_UMISR0-4) can be checked after the operation
is complete, to determine if a correct signature is obtained.
AIE can be set only if DFLASH_MCR[ERS], DFLASH_MCR[PGM] and DFLASH_MCR[EHV] are all low.
0: Array Integrity Checks are not enabled.
1: Array Integrity Checks are enabled.
AID Array Integrity Done
AID will be cleared upon an Array Integrity Check being enabled (to signify the operation is on-going).
Once completed, AID will be set to indicate that the Array Integrity Check is complete. At this time the
MISR (DFLASH_UMISR0-4) can be checked.
0: Array Integrity Check is on-going.
1: Array Integrity Check is done.
Table 27-46. DFLASH_UT0 field descriptions (continued)
Field Description
To Next Page
Loading...
