Freescale Semiconductor MPC5604B - Page 71

MPC5604B/C Microcontroller Reference Manual, Rev. 8
60 Freescale Semiconductor
PH[6] PCR[118] AF0
AF1
AF2
AF3
GPIO[118]
E1UC[8]
—
MA[2]
SIUL
eMIOS_1
—
ADC
I/O
I/O
—
O
M Tristate — — — 136 D5
PH[7] PCR[119] AF0
AF1
AF2
AF3
GPIO[119]
E1UC[9]
CS3_2
MA[1]
SIUL
eMIOS_1
DSPI_2
ADC
I/O
I/O
O
O
M Tristate — — — 137 C5
PH[8] PCR[120] AF0
AF1
AF2
AF3
GPIO[120]
E1UC[10]
CS2_2
MA[0]
SIUL
eMIOS_1
DSPI_2
ADC
I/O
I/O
O
O
M Tristate — — — 138 A5
PH[9]
9
PCR[121] AF0
AF1
AF2
AF3
GPIO[121]
—
TCK
—
SIUL
—
JTAGC
—
I/O
—
I
—
S Input, weak
pull-up
——88127B8
PH[10]
9
PCR[122] AF0
AF1
AF2
AF3
GPIO[122]
—
TMS
—
SIUL
—
JTAGC
—
I/O
—
I
—
S Input, weak
pull-up
——81120B9
1
Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module.
PCR.PA = 00  AF0; PCR.PA = 01  AF1; PCR.PA = 10  AF2; PCR.PA = 11  AF3. This is intended to select
the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the
values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is
reported as “—”.
2
Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by
setting the values of the PSMIO.PADSELx bitfields inside the SIUL module.
3
208 MAPBGA available only as development package for Nexus2+
4
All WKUP pins also support external interrupt capability. See wakeup unit chapter for further details.
5
NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored.
6
“Not applicable” because these functions are available only while the device is booting. Refer to BAM chapter of the
reference manual for details.
7
Value of PCR.IBE bit must be 0
8
Be aware that this pad is used on the MPC5607B 100-pin and 144-pin to provide VDD_HV_ADC and
VSS_HV_ADC1. Therefore, you should be careful in ensuring compatibility between MPC5604B and MPC5607B.
9
Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO.
PC[0:1] are available as JTAG pins (TDI and TDO respectively).
PH[9:10] are available as JTAG pins (TCK and TMS respectively).
If the user configures these JTAG pins in GPIO mode the device is no longer compliant with IEEE 1149.1-2001.
Table 4-3. Functional port pin descriptions (continued)
Port pin
PCR
Alternate function
1
Function
Peripheral
I/O direction
2
Pad type
RESET configuration
Pin number
MPC560xB 64 LQFP MPC560xC 64 LQFP
100 LQFP 144 LQFP
208 MAPBGA
3