RM0090 Ethernet (ETH): media access control (MAC) with DMA controller
Doc ID 018909 Rev 4 1002/1422
Ethernet PTP target time high register (ETH_PTPTTHR)
Address offset: 0x071C
Reset value: 0x0000 0000
This register contains the higher 32 bits of time to be compared with the system time for
interrupt event generation. The Target time high register, along with Target time low register,
is used to schedule an interrupt event (TSARU bit in ETH_PTPTSCR) when the system time
exceeds the value programmed in these registers.
Ethernet PTP target time low register (ETH_PTPTTLR)
Address offset: 0x0720
Reset value: 0x0000 0000
This register contains the lower 32 bits of time to be compared with the system time for
interrupt event generation.
Ethernet PTP time stamp status register (ETH_PTPTSSR)
Address offset: 0x0728
Reset value: 0x0000 0000
This register contains the time stamp status register.
313029282726252423222120191817161514131211109876543210
TTSH
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Bits 31:0 TTSH: Target time stamp high
This register stores the time in seconds. When the time stamp value matches or exceeds
both Target time stamp registers, the MAC, if enabled, generates an interrupt.
313029282726252423222120191817161514131211109876543210
TTSL
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 TTSL: Target time stamp low
This register stores the time in (signed) nanoseconds. When the value of the time stamp
matches or exceeds both Target time stamp registers, the MAC, if enabled, generates an
interrupt.
313029282726252423222120191817161514131211109876543210
Reserved
TSTTR
TSSO
ro ro
Bits 31:2 Reserved, must be kept at reset value.
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