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ST STM32F40 Series User Manual

ST STM32F40 Series
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USB on-the-go high-speed (OTG_HS) RM0090
1287/1422 Doc ID 018909 Rev 4
transfers, the HS_OTG host continues fetching the next packet (up to the value
specified in the MC field) before switching to the next channel.
c) The OTG_HS host attempts to send the OUT token at the beginning of the next
odd frame/micro-frame.
d) After successfully transmitting the packet, the OTG_HS host generates a CHH
interrupt.
e) In response to the CHH interrupt, reinitialize the channel for the next transfer.
Interrupt IN transactions in DMA mode
The sequence of operations (channelx) is as follows:
a) Initialize and enable channel x as explained in Section : Channel initialization.
b) The OTG_HS host writes an IN request to the request queue as soon as the
channel x gets the grant from the arbiter (round-robin with fairness). In high-
bandwidth transfers, the OTG_HS host writes consecutive writes up to MC times.
c) The OTG_HS host attempts to send an IN token at the beginning of the next (odd)
frame/micro-frame.
d) As soon the packet is received and written to the receive FIFO, the OTG_HS host
generates a CHH interrupt.
e) In response to the CHH interrupt, reinitialize the channel for the next transfer.
Isochronous OUT transactions in DMA mode
a) Initialize and enable channel x as explained in Section : Channel initialization.
b) The OTG_HS host starts fetching the first packet as soon as the channel is
enabled, and writes the OUT request along with the last DWORD fetch. In high-
bandwidth transfers, the OTG_HS host continues fetching the next packet (up to
the value specified in the MC field) before switching to the next channel.
c) The OTG_HS host attempts to send an OUT token at the beginning of the next
(odd) frame/micro-frame.
d) After successfully transmitting the packet, the HS_OTG host generates a CHH
interrupt.
e) In response to the CHH interrupt, reinitialize the channel for the next transfer.
Isochronous IN transactions in DMA mode
The sequence of operations ((channel x) is as follows:
a) Initialize and enable channel x as explained in Section : Channel initialization.
b) The OTG_HS host writes an IN request to the request queue as soon as the
channel x gets the grant from the arbiter (round-robin with fairness). In high-

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ST STM32F40 Series Specifications

General IconGeneral
BrandST
ModelSTM32F40 Series
CategoryMicrocontrollers
LanguageEnglish

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