RM0090 Flexible static memory controller (FSMC)
Doc ID 018909 Rev 4 1352/1422
Bit 11 WAITCFG: Wait timing configuration.
The NWAIT signal indicates whether the data from the memory are valid or if a wait
state must be inserted when accessing the Flash memory in synchronous mode. This
configuration bit determines if NWAIT is asserted by the memory one clock cycle
before the wait state or during the wait state:
0: NWAIT signal is active one data cycle before wait state (default after reset),
1: NWAIT signal is active during wait state (not for Cellular RAM).
Bit 10 WRAPMOD: Wrapped burst mode support.
Defines whether the controller will or not split an AHB burst wrap access into two linear
accesses. Valid only when accessing memories in burst mode
0: Direct wrapped burst is not enabled (default after reset),
1: Direct wrapped burst is enabled.
Note: This bit has no effect as the CPU and DMA cannot generate wrapping burst
transfers.
Bit 9 WAITPOL: Wait signal polarity bit.
Defines the polarity of the wait signal from memory. Valid only when accessing the
memory in burst mode:
0: NWAIT active low (default after reset),
1: NWAIT active high.
Bit 8 BURSTEN: Burst enable bit.
This bit enables/disables the synchronous burst access during read operations. It is
valid only with synchronous burst memories:
0: Burst access mode disabled (default after reset)
1: Burst access mode enable
Bit 7 Reserved, must be kept at reset value.
Bit 6 FACCEN: Flash access enable
Enables NOR Flash memory access operations.
0: Corresponding NOR Flash memory access is disabled
1: Corresponding NOR Flash memory access is enabled (default after reset)
Bits 5:4 MWID: Memory databus width.
Defines the external memory device width, valid for all type of memories.
00: 8 bits,
01: 16 bits (default after reset),
10: reserved, do not use,
11: reserved, do not use.
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