RM0090 Revision history
Doc ID 018909 Rev 4 1416/1422
19-Oct-2012
2
(continued)
RTC:
Updated Figure 222: RTC block diagram.
Added formula to compute
fck_apre in Section 23.3.1: Clock and
prescalers
.
Updated Section 23.3.9: RTC reference clock detection.
Updated Section : RTC register write protection.
Added RTC_SSR shadow register in Section 23.3.6: Reading the
calendar.
Updated description of DC[4:0] bits in Section 23.6.7: RTC
calibration register (RTC_CALIBR).
Renamed RTC_BKxR into RTC_BKPxR in Table 99: RTC register
map and reset values.
Added power-on reset value and changed reset value to system
reset value in Section 23.6.11: RTC sub second register
(RTC_SSR).
Updated definition of ALARMOUTTYPE in Section 23.6.17: RTC
tamper and alternate function configuration register (RTC_TAFCR).
I2C:
Modified Section 25.3.8: DMA requests.
Updated bit 14 description in Section 25.6.3: I2C Own address
register 1 (I2C_OAR1)).
Updated definition of PE bit and note related to SWRST bit; moved
note related to STOP bit to the whole register in Section 25.6.1: I2C
Control register 1 (I2C_CR1).
USART:
Section 26.6.6: Control register 3 (USART_CR3)): removed notes
related to UART5 in DMAT and DMAR description.
Updated TTable 116: Error calculation for programmed baud rates at
fPCLK = 42 MHz or fPCLK = 84 Hz, oversampling by 16 and
Table 117: Error calculation for programmed baud rates at fPCLK =
42 MHz or fPCLK = 84 MHz, oversampling by 8.
SPI/I2S:
Updated Section 27.1: SPI introduction.
Changed I2S simplex communication/mode to half-duplex
communication/mode. Updated flags in reception/transmission
modes in Section 27.2.2: I2S features. Added Frame error flag in
Table 126: I2S interrupt requests.
Added register access in Section 27.5: SPI and I2S registers.
Updated ERRIE definition in Section 27.5.2: SPI control register 2
(SPI_CR2).
Renamed TIFRFE to FRE and definition updated in Section 27.5.3:
SPI status register (SPI_SR).
Table 240. Document revision history
Date Version Changes
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