ST STM32F40 Series User Manual

Revision history RM0090
1415/1422 Doc ID 018909 Rev 4
19-Oct-2012
2
(continued)
General purpose timers (TIM2 to TIM5)
Removed all references to “repetition counter”.
Added Figure 119: General-purpose timer block diagram.
Updated 16-bit prescaler range in Section 15.2: TIM2 to TIM5 main
features.
External clock mode 2 ETR restricted to TIM2 to TIM4 in
Section 15.3.3: Clock selection and Section 15.3.6: PWM input
mode.
Updated Section 15.3.9: PWM mode and Section 15.3.11: Clearing
the OCxREF signal on an external event.
Updated Figure 159: Master/Slave timer example to change ITR1 to
ITR0.
Updated read and write access to registers in Section 15.4: TIM2 to
TIM5 registerss.
Restored bits 15 to 8 of TIMx_SMCR as well as Table 7 6 : T I M x
internal trigger connection in Section 14.4.3.
Removed note 1 related to OC1M bits in Section 15.4.13: TIMx
capture/compare register 1 (TIMx_CCR1).
Updated TIMx_CCER bit description for TIM2 to TIM5 in
Section 15.4.9: TIMx capture/compare enable register
(TIMx_CCER).
General purpose timers (TIM9 to TIM14)
Updated 16-bit prescaler range in Section 16.2.1: TIM9/TIM12 main
features and Section 16.3: TIM10/TIM11 and TIM13/TIM14 main
features.
Updated Figure 166: General-purpose timer block diagram
(TIM10/11/13/14)) to remove TRGO trigger controller output.
Added register access in Section 16.5: TIM9 and TIM12 registers
and Section 16.6: TIM10/11/13/14 registers.
Basic timers (TIM6 and TIM7)
Removed all references to “repetition counter”.
Updated 16-bit prescaler range in Section 17.2: TIM6&TIM7 main
features.
HASH:
Updated Section 22.3.1: Duration of the processing.
RNG:
Updated Section 21.1: RNG introduction.
Table 240. Document revision history
Date Version Changes

ST STM32F40 Series Specifications

General

Brand	ST
Model	STM32F40 Series
Category	Microcontrollers
Language	English