EasyManuals Logo

ST STM32F40 Series User Manual

ST STM32F40 Series
1422 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #162 background imageLoading...
Page #162 background image
RM0090 Reset and clock control for (RCC)
Doc ID 018909 Rev 4 162/1422
Bit 21 DMA1LPEN: DMA1 clock enable during Sleep mode
Set and cleared by software.
0: DMA1 clock disabled during Sleep mode
1: DMA1 clock enabled during Sleep mode
Bit 20 Reserved, must be kept at reset value.
Bit 19 SRAM3LPEN: SRAM3 interface clock enable during Sleep mode
Set and cleared by software.
0: SRAM3 interface clock disabled during Sleep mode
1: SRAM3 interface clock enabled during Sleep mode
Bit 18 BKPSRAMLPEN: Backup SRAM interface clock enable during Sleep mode
Set and cleared by software.
0: Backup SRAM interface clock disabled during Sleep mode
1: Backup SRAM interface clock enabled during Sleep mode
Bit 17 SRAM2LPEN: SRAM2 interface clock enable during Sleep mode
Set and cleared by software.
0: SRAM2 interface clock disabled during Sleep mode
1: SRAM2 interface clock enabled during Sleep mode
Bit 16 SRAM1LPEN: SRAM1interface clock enable during Sleep mode
Set and cleared by software.
0: SRAM1 interface clock disabled during Sleep mode
1: SRAM1 interface clock enabled during Sleep mode
Bit 15 FLITFLPEN: Flash interface clock enable during Sleep mode
Set and cleared by software.
0: Flash interface clock disabled during Sleep mode
1: Flash interface clock enabled during Sleep mode
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 CRCLPEN: CRC clock enable during Sleep mode
Set and cleared by software.
0: CRC clock disabled during Sleep mode
1: CRC clock enabled during Sleep mode
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 GPIOILPEN: IO port I clock enable during Sleep mode
Set and cleared by software.
0: IO port I clock disabled during Sleep mode
1: IO port I clock enabled during Sleep mode
Bit 7 GPIOHLPEN: IO port H clock enable during Sleep mode
Set and cleared by software.
0: IO port H clock disabled during Sleep mode
1: IO port H clock enabled during Sleep mode
Bits 6 GPIOGLPEN: IO port G clock enable during Sleep mode
Set and cleared by software.
0: IO port G clock disabled during Sleep mode
1: IO port G clock enabled during Sleep mode

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the ST STM32F40 Series and is the answer not in the manual?

ST STM32F40 Series Specifications

General IconGeneral
BrandST
ModelSTM32F40 Series
CategoryMicrocontrollers
LanguageEnglish

Related product manuals