RM0090 Serial peripheral interface (SPI)
Doc ID 018909 Rev 4 838/1422
Bit 10 RXONLY: Receive only
This bit combined with the BIDImode bit selects the direction of transfer in 2-line
unidirectional mode. This bit is also useful in a multislave system in which this particular
slave is not accessed, the output from the accessed slave is not corrupted.
0: Full duplex (Transmit and receive)
1: Output disabled (Receive-only mode)
Note: Not used in I
2
S mode
Bit 9 SSM: Software slave management
When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit.
0: Software slave management disabled
1: Software slave management enabled
Note: Not used in I
2
S mode and SPI TI mode
Bit 8 SSI: Internal slave select
This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the
NSS pin and the IO value of the NSS pin is ignored.
Note: Not used in I
2
S mode and SPI TI mode
Bit 7 LSBFIRST: Frame format
0: MSB transmitted first
1: LSB transmitted first
Note: This bit should not be changed when communication is ongoing.
Not used in I
2
S mode and SPI TI mode
Bit 6 SPE: SPI enable
0: Peripheral disabled
1: Peripheral enabled
Note: 1- Not used in I
2
S mode.
Note: 2- When disabling the SPI, follow the procedure described in Section 27.3.8: Disabling the
SPI.
Bits 5:3 BR[2:0]: Baud rate control
000: f
PCLK
/2100: f
PCLK
/32
001: f
PCLK
/4101: f
PCLK
/64
010: f
PCLK
/8110: f
PCLK
/128
011: f
PCLK
/16111: f
PCLK
/256
Note: These bits should not be changed when communication is ongoing.
Not used in I
2
S mode
Bit 2 MSTR: Master selection
0: Slave configuration
1: Master configuration
Note: This bit should not be changed when communication is ongoing.
Not used in I
2
S mode
Bit1 CPOL: Clock polarity
0: CK to 0 when idle
1: CK to 1 when idle
Note: This bit should not be changed when communication is ongoing.
Not used in I
2
S mode and SPI TI mode
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