Ethernet (ETH): media access control (MAC) with DMA controller RM0090
995/1422 Doc ID 018909 Rev 4
Ethernet MMC transmitted good frames after more than a single collision
counter register (ETH_MMCTGFMSCCR)
Address offset: 0x0150
Reset value: 0x0000 0000
This register contains the number of successfully transmitted frames after more than a
single collision in Half-duplex mode.
Ethernet MMC transmitted good frames counter register (ETH_MMCTGFCR)
Address offset: 0x0168
Reset value: 0x0000 0000
This register contains the number of good frames transmitted.
Ethernet MMC received frames with CRC error counter register
(ETH_MMCRFCECR)
Address offset: 0x0194
Reset value: 0x0000 0000
This register contains the number of frames received with CRC error.
313029282726252423222120191817161514131211109876543210
TGFMSCC
rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr
Bits 31:0 TGFMSCC: Transmitted good frames more single collision counter
Transmitted good frames after more than a single collision counter
313029282726252423222120191817161514131211109876543210
TGFC
rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr
Bits 31:0 TGFC: Transmitted good frames counter
313029282726252423222120191817161514131211109876543210
RFCEC
rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr
Bits 31:0 RFCEC: Received frames CRC error counter
Received frames with CRC error counter
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