Freescale Semiconductor MPC5604B - 4. External interrupts

MPC5604B/C Microcontroller Reference Manual, Rev. 8
8 Freescale Semiconductor
15.3 Block diagram ...............................................................................................................................263
15.4 Features .........................................................................................................................................263
15.4.1 Instruction unit features ................................................................................................264
15.4.2 Integer unit features ......................................................................................................264
15.4.3 Load/Store unit features ...............................................................................................265
15.4.4 e200z0h system bus features ........................................................................................265
15.4.5 Nexus 2+ features .........................................................................................................265
15.5 Core registers and programmer’s model .......................................................................................266
Chapter 16
Interrupt Controller (INTC)
16.1 Introduction ...................................................................................................................................269
16.2 Features .........................................................................................................................................269
16.3 Block diagram ...............................................................................................................................270
16.4 Modes of operation ........................................................................................................................271
16.4.1 Normal mode ................................................................................................................271
16.5 Memory map and register description ...........................................................................................272
16.5.1 Module memory map ...................................................................................................272
16.5.2 Register description ......................................................................................................273
16.6 Functional description ...................................................................................................................280
16.6.1 Interrupt request sources ...............................................................................................289
16.6.2 Priority management ....................................................................................................289
16.6.3 Handshaking with processor .........................................................................................291
16.7 Initialization/application information ............................................................................................293
16.7.1 Initialization flow .........................................................................................................293
16.7.2 Interrupt exception handler ...........................................................................................293
16.7.3 ISR, RTOS, and task hierarchy .....................................................................................295
16.7.4 Order of execution ........................................................................................................296
16.7.5 Priority ceiling protocol ................................................................................................297
16.7.6 Selecting priorities according to request rates and deadlines .......................................297
16.7.7 Software configurable interrupt requests ......................................................................298
16.7.8 Lowering priority within an ISR ..................................................................................299
16.7.9 Negating an interrupt request outside of its ISR ..........................................................299
16.7.10 Examining LIFO contents ............................................................................................300
Chapter 17
Crossbar Switch (XBAR)
17.1 Introduction ...................................................................................................................................301
17.2 Block diagram ...............................................................................................................................301
17.3 Overview .......................................................................................................................................302
17.4 Features .........................................................................................................................................302
17.5 Modes of operation ........................................................................................................................302
17.5.1 Normal mode ................................................................................................................302
17.5.2 Debug mode ..................................................................................................................302
17.6 Functional description ...................................................................................................................302