Freescale Semiconductor MPC5604B - Page 22

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 11
22.1.2 FlexCAN module features ............................................................................................424
22.1.3 Modes of operation .......................................................................................................425
22.2 External signal description ............................................................................................................425
22.2.1 Overview ......................................................................................................................425
22.2.2 Signal descriptions ........................................................................................................426
22.3 Memory map and register description ...........................................................................................426
22.3.1 FlexCAN memory mapping .........................................................................................426
22.3.2 Message buffer structure ..............................................................................................428
22.3.3 Rx FIFO structure .........................................................................................................431
22.3.4 Register description ......................................................................................................433
22.4 Functional description ...................................................................................................................451
22.4.1 Overview ......................................................................................................................451
22.4.2 Local priority transmission ...........................................................................................452
22.4.3 Transmit process ...........................................................................................................452
22.4.4 Arbitration process .......................................................................................................453
22.4.5 Receive process ............................................................................................................454
22.4.6 Matching process ..........................................................................................................455
22.4.7 Data coherence .............................................................................................................456
22.4.8 Rx FIFO ........................................................................................................................459
22.4.9 CAN protocol related features ......................................................................................460
22.4.10 Modes of operation details ...........................................................................................464
22.4.11 Interrupts .......................................................................................................................465
22.4.12 Bus interface .................................................................................................................465
22.5 Initialization/Application information ...........................................................................................466
22.5.1 FlexCAN initialization sequence ..................................................................................466
22.5.2 FlexCAN addressing and SRAM size configurations ..................................................467
Chapter 23
Deserial Serial Peripheral Interface (DSPI)
23.1 Introduction ...................................................................................................................................469
23.2 Features .........................................................................................................................................470
23.3 Modes of operation ........................................................................................................................471
23.3.1 Master mode .................................................................................................................471
23.3.2 Slave mode ...................................................................................................................471
23.3.3 Module Disable mode ...................................................................................................471
23.3.4 Debug mode ..................................................................................................................472
23.4 External signal description ............................................................................................................472
23.4.1 Signal overview ............................................................................................................472
23.4.2 Signal names and descriptions ......................................................................................472
23.5 Memory map and register description ...........................................................................................474
23.5.1 Memory map ................................................................................................................474
23.5.2 DSPI Module Configuration Register (DSPIx_MCR) .................................................475
23.5.3 DSPI Transfer Count Register (DSPIx_TCR) ..............................................................478
23.5.4 DSPI Clock and Transfer Attributes Registers 0–5 (DSPIx_CTARn) .........................478
23.5.5 DSPI Status Register (DSPIx_SR) ...............................................................................486