Freescale Semiconductor MPC5604B - Chapter 4 Timer Modules; 1. Introduction

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 15
29.3 Modes of operation ........................................................................................................................742
29.4 External signal description ............................................................................................................742
29.5 Memory map and register description ...........................................................................................742
29.5.1 Memory map ................................................................................................................743
29.5.2 Register description ......................................................................................................744
29.6 Functional description ...................................................................................................................746
29.6.1 General .........................................................................................................................746
29.6.2 Change lock settings .....................................................................................................746
29.6.3 Access errors ................................................................................................................750
29.7 Reset ..............................................................................................................................................750
29.8 Protected registers .........................................................................................................................750
Chapter 30
Software Watchdog Timer (SWT)
30.1 Overview .......................................................................................................................................755
30.2 Features .........................................................................................................................................755
30.3 Modes of operation ........................................................................................................................755
30.4 External signal description ............................................................................................................756
30.5 Memory map and register description ...........................................................................................756
30.5.1 Memory map ................................................................................................................756
30.5.2 Register description ......................................................................................................757
30.6 Functional description ...................................................................................................................761
Chapter 31
Error Correction Status Module (ECSM)
31.1 Introduction ...................................................................................................................................763
31.2 Overview .......................................................................................................................................763
31.3 Features .........................................................................................................................................763
31.4 Memory map and register description ...........................................................................................763
31.4.1 Memory map ................................................................................................................763
31.4.2 Register description ......................................................................................................764
31.4.3 Register protection ........................................................................................................783
Chapter 32
IEEE 1149.1 Test Access Port Controller (JTAGC)
32.1 Introduction ...................................................................................................................................787
32.2 Block diagram ...............................................................................................................................787
32.3 Overview .......................................................................................................................................787
32.4 Features .........................................................................................................................................788
32.5 Modes of operation ........................................................................................................................788
32.5.1 Reset .............................................................................................................................788
32.5.2 IEEE 1149.1-2001 defined test modes .........................................................................788
32.6 External signal description ............................................................................................................789
32.7 Memory map and register description ...........................................................................................790
32.7.1 Instruction Register ......................................................................................................790